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MM74HCT240 * MM74HCT244 Inverting Octal 3-STATE Buffer * Octal 3-STATE Buffer
February 1984 Revised May 2005
MM74HCT240 * MM74HCT244 Inverting Octal 3-STATE Buffer * Octal 3-STATE Buffer
General Description
The MM74HCT240 and MM74HCT244 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed inverting and non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the low power consumption of CMOS. All three devices are TTL input compatible and have a fanout of 15 LS-TTL equivalent inputs. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. The MM74HCT240 is an inverting buffer and the MM74HCT244 is a non-inverting buffer. Each device has two active low enables (1G and 2G), and each enable independently controls 4 buffers. All inputs are protected from damage due to static discharge by diodes to VCC and Ground.
Features
s TTL input compatible s Typical propagation delay: 14 ns s 3-STATE outputs for connection to system buses s Low quiescent current: 80 PA s High output drive current: 6 mA (min)
Ordering Code:
Order Number MM74HCT240WM MM74HCT240SJ MM74HCT240MTC MM74HCT240N MM74HCT244WM MM74HCT244SJ MM74HCT244MTC MM74HCT244N Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View MM74HCT240
Top View MM74HCT244
(c) 2005 Fairchild Semiconductor Corporation
DS005365
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MM74HCT240 * MM74HCT244
Truth Tables
MM74HCT240 1G L L H H
H HIGH Level
MM74HCT244 2A L H L H
Z
1A L H L H
L
1Y H L Z Z
2G L L H H
2Y H L Z Z
High Impedance
1G L L H H
1A L H L H
1Y L H Z Z
2G L L H H
2A L H L H
2Y L H Z Z
LOW Level
Logic Diagrams
MM74HCT240 MM74HCT244
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MM74HCT240 * MM74HCT244
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: 12 mW/qC from 65qC to 85qC.
0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC
Max 5.5 VCC
Units V V
4.5 0
40
85
qC
DC Electrical Characteristics
VCC 5V r10% (unless otherwise specified) Parameter Minimum HIGH Level Input Voltage VIL VOH Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN-EE |IOUT | |IOUT | |IOUT | VOL Maximum LOW Level Voltage VIN |IOUT | |IOUT | |IOUT | IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN VOUT G G VIN IOUT VIN VIH VIL VCC or GND 0 PA 2.4V or 0.5V (Note 4) 0.6 1.0 1.3 1.5 mA 4.0 40 160 VIH or VIL 20 PA 6.0 mA, VCC 7.2 mA, VCC VIH or VIL 20 PA 6.0 mA, VCC 7.2 mA, VCC VCC or GND, VCC or GND 4.5V 5.5V 0 0.2 0.2 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.4 0.4 V V V 4.5V 5.5V VCC 4.2 5.2 VCC0.1 3.98 4.98 VCC0.1 3.84 4.84 VCC0.1 3.7 4.7 V V V 0.8 0.8 0.8 V Conditions TA Typ 2.0 25qC TA Symbol VIH
40 to 85qC TA 55q to 125qC
Guaranteed Limits 2.0 2.0
Units V
r0.05 r0.25
r0.5 r2.5
r1.0 r10
PA PA
VIH or VIL
PA
Note 4: Measured per input. All other inputs at VCC or GND.
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MM74HCT240 * MM74HCT244
AC Electrical Characteristics
MM74HCT240, MM74HCT244 VCC Symbol tPHL, tPLH tPZL, tPZH tPLZ, tPHZ
5.0V, tr
tf
6 ns, TA 25qC (unless otherwise specified)
Conditions CL CL RL CL RL 45 pF 45 pF 1 k: 5 pF 1 k: 16 25 ns Typ 14 20 Guaranteed Limits 18 30 Units ns ns
Parameter Maximum Output Propagation Delay Maximum Output Enable Time Maximum Output Disable Time
AC Electrical Characteristics
MM74HCT240, MM74HCT244 VCC Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tTHL, tTLH CIN COUT CPD Parameter Maximum Output Propagation Delay Maximum Output Enable Time Maximum Output Disable Time Maximum Output Rise and Fall Time Maximum Input Capacitance Maximum Output Capacitance Power Dissipation Capacitance (Note 5) G G (per buffer) V CC, G GND, G GND VCC 5 90
C PD VCC2 f ICC VCC, and the no load dynamic current consumption,
5.0V r 10%, tr
tf 6 ns (unless otherwise specified)
TA Typ 14 20 CL CL 50 pF 150 pF 21 26 16 6 10 15 20 28 30 42 25 12 15 20 25qC TA
Conditions CL CL RL RL CL CL 50 pF 150 pF 1 k: 1 k: 50 pF 50 pF
40 to 85qC TA 55q to 125qC
Guaranteed Limits 25 35 38 53 32 15 15 20 30 42 45 63 38 18 15 20
Units ns ns ns ns ns ns pF pF
pF pF
Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f I CC.
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MM74HCT240 * MM74HCT244
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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MM74HCT240 * MM74HCT244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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MM74HCT240 * MM74HCT244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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MM74HCT240 * MM74HCT244 Inverting Octal 3-STATE Buffer * Octal 3-STATE Buffer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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